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Renesas Electronics /R7FA6T1AD /DBG /TRACECTR

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Interpret as TRACECTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)ENETBFULL

ENETBFULL=0

Description

Trace Control Register

Fields

ENETBFULL

Enable bit for halt request by ETB full

0 (0): ETB full does not cause CPU halt

1 (1): ETB full cause CPU halt

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data